1. Field of the Invention
This invention relates in general to a signal processing device such as a digital filter utilizing a redundant binary expression. More particularly, it relates to a signal processing device adapted for converting digital input signals expressed in a redundant binary expression into corresponding analog signals. The invention has particular applicability to a digital filter.
2. Description of the Background Art
As is well known, the complement expression of 2 is widely used for arithmetic operations in various data processing apparatuses besides digital computers. The reason for this is that by using the complement expression of 2, a subtraction can be carried out by an addition of a summand and an addend both represented in 2's complement expression. Therefore, it becomes possible to carry out all arithmetic operations by addition in principle. Further, it is noted that the conversion of data represented in binary expression into data represented in 2's complement expression is very easy, as described in detail in a textbook entitled "Digital Logic and Computer Design" by M. MORRIS MANO copyrighted in 1979 (pp. 38 to pp. 42 in Japanese version).
When a figure X expressed in 2's complement expression, that is Xn, X (n-1), . . . , Xl, the figure X is expressed by the following formula (1); ##EQU1##
wherein Xi is either 1 or 0. Thus, domain of the figure X may be defined by the following formula (2). EQU -2.sup.n-1 +1.ltoreq.X.ltoreq.2.sup.n-1 (2)
On the other hand, there is so far known a method of expressing data signals by redundant binary expression. A detailed description pertinent to the redundant binary expression can be found in, for example, an article of IRE September 1961 entitled "Signed-Digit Number Representations for FAST Parallel Arithmetic" by A. AVIZIENIS.
A given number Y, when expressed by the redundant binary expression Yn, Y(n-1), . . . , Yl, may be defined by the following formula 3; ##EQU2## wherein Yi may assume -1, 0 or 1.
When the figure X is expressed by the 2's complement expression, there exist only one way of expression of Xn, X(n-1), . . . , Xl. However, when employing the redundant binary expression, a given decimal quantity 5 may be expressed in several ways, as shown by the following formulas; EQU 5=0 1 0 1 =0 . 2.sup.3 +1 . 2.sup.2 +0 . 2.sup.1 +1 . 2.sup.0 (4a) EQU 5=0 1 1 -1 =0 . 2.sup.3 +1 . 2.sup.2 +1 . 2.sup.1 -1 .2.sup.0 (4b) EQU 5=1 0 -1 -1 =1 . 2.sup.3 +0 . 2.sup.2 -1 . 2.sup.1 -1 . 2.sup.0 (4c) EQU 5=1 0 31 1 -1 =1 . 2.sup.3 +0 . 2.sup.2 -1 . 2.sup.1 -1 . 2.sup.0 (4c) EQU 5=1 -1 1 -1 =1 . 2.sup.3 -1 . 2.sup.2 +1 . 2.sup.1 -1 . 2.sup.0 (4d)
In this manner, when the data is expressed by the redundant binary expression, a given decimal quantity may be expressed in several ways, so that there is no necessity of carry transfer when performing the operation of addition or subtraction. Thus an advantage is derived that the carry signals are no longer required and a high speed addition or subtraction can be performed. This will be more clearly understood by the description of the following example.
FIG. 9A shows an idea of an addition of two data expressed in the 2's complement expression. FIG. 9B shows an idea of an addition of two data expressed in the redundant binary expression. An addition of 11 (=A) and 93 (=B) in decimal quantity is shown as an example in these figures. Referring to FIG. 9A, the data Ac and Bc expressed in 2's complement expression are added resulting in the data Sc represented in 2's complement. As is denoted by an arrow in FIG. 9A, 5 carries are generated in the lower 6 bits.
Meanwhile, referring to FIG. 9B, the data Ar and Br each expressed in redundant binary expression are added, resulting the data Sr represented in the redundant binary expression. In this calculation, the rule in association with the carry C and an intermediate sum M shown in FIG. 9C is applied.
FIG. 9C is a table defining the relation between each of the summand ai, addend bi, summand ai-1 and an addend bi-1 of 1 digit lower rank for finding respective digits ci and mi of carry and intermediate sum. By applying the relation shown in FIG. 9C, the carry C and the intermediate sum M shown in FIG. 9B can be provided. Therefore, the result of addition of the data Ar and Br is provided by adding the carry data C and the intermediate sum data M. In this addition, carry transfer is not generated, and accordingly, the carry transfer signal becomes unnecessary. This method of calculation is described in detail in an article entitled "A VLSI-Oriented High-Speed Multiplier Using a Redundant Binary Addition Tree" (1983 Journal of Institute of Electronics and Communication Engineers Vol. J66-D No.6).
It is noted that, when a figure expressed in the 2's complement expression is converted into a figure expressed in the redundant binary expression, it only suffices to invert the sign of the most significant bit, that is, the sign bit, of the figure expressed in the 2's complement expression. This means that the procedure of conversion can be simplified significantly.
For example, when the sign bit (Xn) is 1, the value of the given figure X is as follows. ##EQU3## By determining the sign of the sign bit of this figure, another figure Y' is as follows. ##EQU4## The figure Y' is equal to the figure Y' expressed by the formula (3). In this manner, a figure expressed in the redundant binary expression may be derived easily by simply inverting the sign of the sign bit.
Conversely, when converting a figure expressed in the redundant binary expression into a figure expressed in the 2's complement expression, it is necessary to perform addition or subtraction with respect to the figure expressed in the 2's complement expression, since there may be the cases wherein Yi is 1 or -1. That is, for obtaining a figure expressed in the 2's complement expression, it is necessary to perform an arithmetic operation of the following formula. 2's Complement Expression ##EQU5##
It is pointed out that, when performing the arithmetic operation shown by the formula (5), it is necessary to perform an addition accompanied by carry transfers.
FIG. 10 is a block diagram showing the general arrangement of a digital filter as an example of a conventional signal processing device. Referring to FIG. 8, this digital filter includes an A/D converter 21 for converting input analog signals into corresponding digital signals, an arithmetic operation section 25 for performing an arithmetic operation as a digital filter, and a D/A converter 26 for converting the digital signals from the arithmetic operation section 25 into analog signals. The arithmetic operation section 25 includes a clock generator 71, a coefficient memory 72 activated responsive to clock signals generated in the clock generator 71, a multiplication unit 73, and a delay element 74.
The arithmetic operation section 25 of the digital filter shown in FIG. 8 performs an arithmetic operation on data expressed in 2's complement expression. That is, the A/D converter 21 converts the analog signals into digital data expressed in 2's complement expression to transmit the digital data to the arithmetic operation section 25. The output data outputted from the arithmetic operation section 25 are also similarly expressed into 2's complement expression. Thus, the D/A converter 26 converts the two data from the arithmetic operation section 25 expressed in 2's complement expression into analog signals.
In the conventional arithmetic operation device for signals shown in FIG. 8, since the arithmetic operation in the operation section 25 is performed with respect to the data expressed in the 2's complement expression, it is necessary to perform carry transfers at the time of addition or subtraction, so that a high speed arithmetic operation cannot be achieved.
Even supposing that a circuit for performing the arithmetic operation on data expressed in the redundant binary expression is provided in the arithmetic operation section 25, it is necessary to convert the manner of expression of output data from the arithmetic operation section 25 from the redundant binary expression into the 2's complement expression. This means that a converting circuit for the manner of expression need be provided a new between the arithmetic operation section 25 and the D/A converter 26. As discussed hereinabove, an addition accompanied by carry transfers need be performed at the time of conversion of the data expressed by the formula (5). The result is that, even supposing that the arithmetic operation on the data expressed in the redundant binary expression is performed in the arithmetic operation section, it takes much time to convert the data of the results of the arithmetic operation into the 2's complement expression, so that the high speed arithmetic operation cannot as a whole be achieved.
A prior art having pertinence to this invention may be seen in IEEE International Solid State Circuit Conference, Digest of Technical Papers, pp. 152, 153, 342 and 343, 1988. This prior art example also discloses a high speed digital multiplier using a redundant binary expression. In this high speed digital multiplier, multiplication is carried out on data represented in the redundant binary expression, and thereafter the calculated data are converted into 2's complement expression.